VLSI Design: VHDL      

Hardware Description Language (Front End VLSI)            

Course Outline: 

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

  • Introduction
  • Structural VHDL
  • Behavioral VHDL
  • RTL Code
  • Data Type
  • Configuration & Package
  • VHDL Library Management
  • VHDL Simulation & Synthesis Flow
  • VHDL synthesizable code for Logic Components (Combinational & Sequential)
  • Delay Simulation
  • Timing Analysis
  • Test Bench Creation
  • FPGA Synthesis
  • if/case/loop/when-else/with-select/port-mapping/ components/sub-file/clock generation coding tricks
  • UCF Creation
  • FPGA Architecture
  • Introduction to FPGA Practical World
  • Spartan-3A, Spartan-3E, Basys-2 Board Pin Configuration
  • Hands on practical with FPGA
  • Using ISP method FPGA downloading Process
  • FSM Methods
  • LCD and DC motor Interfacing